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<div class="header">
  <div class="summary">
<a href="#pub-attribs">Data Fields</a>  </div>
  <div class="headertitle"><div class="title">TPIU_Type Struct Reference</div></div>
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<div class="contents">

<p>Structure type to access the Trace Port Interface Register (TPI).  
 <a href="structTPIU__Type.html#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a7d6b32aac67b18ded927392a83245ace"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structTPIU__Type.html#a7d6b32aac67b18ded927392a83245ace">ACPR</a></td></tr>
<tr class="memdesc:a7d6b32aac67b18ded927392a83245ace"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register.  <br /></td></tr>
<tr class="separator:a7d6b32aac67b18ded927392a83245ace"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a65a5db46df2d49e4b7d0cb2a91f362fc"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structTPIU__Type.html#a65a5db46df2d49e4b7d0cb2a91f362fc">CLAIMCLR</a></td></tr>
<tr class="memdesc:a65a5db46df2d49e4b7d0cb2a91f362fc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xFA4 (R/W) Claim tag clear.  <br /></td></tr>
<tr class="separator:a65a5db46df2d49e4b7d0cb2a91f362fc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acc42ffa5fe661df6339dc3e9a61f57d7"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structTPIU__Type.html#acc42ffa5fe661df6339dc3e9a61f57d7">CLAIMSET</a></td></tr>
<tr class="memdesc:acc42ffa5fe661df6339dc3e9a61f57d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xFA0 (R/W) Claim tag set.  <br /></td></tr>
<tr class="separator:acc42ffa5fe661df6339dc3e9a61f57d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6362b723d89dd97aa71d72e3ce94465b"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structTPIU__Type.html#a6362b723d89dd97aa71d72e3ce94465b">CSPSR</a></td></tr>
<tr class="memdesc:a6362b723d89dd97aa71d72e3ce94465b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x004 (R/W) Current Parallel Port Size Register.  <br /></td></tr>
<tr class="separator:a6362b723d89dd97aa71d72e3ce94465b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afc5d82ae575c1437b46d7b3928357dc3"><td class="memItemLeft" align="right" valign="top">__IM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structTPIU__Type.html#afc5d82ae575c1437b46d7b3928357dc3">DEVID</a></td></tr>
<tr class="memdesc:afc5d82ae575c1437b46d7b3928357dc3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xFC8 (R/ ) TPIU_DEVID.  <br /></td></tr>
<tr class="separator:afc5d82ae575c1437b46d7b3928357dc3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a06cd44ff1439b93aff76a8d155d7b465"><td class="memItemLeft" align="right" valign="top">__IM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structTPIU__Type.html#a06cd44ff1439b93aff76a8d155d7b465">DEVTYPE</a></td></tr>
<tr class="memdesc:a06cd44ff1439b93aff76a8d155d7b465"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xFCC (R/ ) TPIU_DEVTYPE.  <br /></td></tr>
<tr class="separator:a06cd44ff1439b93aff76a8d155d7b465"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa151f4dedec63032b8d66830529bdbd4"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structTPIU__Type.html#aa151f4dedec63032b8d66830529bdbd4">FFCR</a></td></tr>
<tr class="memdesc:aa151f4dedec63032b8d66830529bdbd4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x304 (R/W) Formatter and Flush Control Register.  <br /></td></tr>
<tr class="separator:aa151f4dedec63032b8d66830529bdbd4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a72599d9a15ce1965a2df71d10817f5f8"><td class="memItemLeft" align="right" valign="top">__IM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structTPIU__Type.html#a72599d9a15ce1965a2df71d10817f5f8">FFSR</a></td></tr>
<tr class="memdesc:a72599d9a15ce1965a2df71d10817f5f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x300 (R/ ) Formatter and Flush Status Register.  <br /></td></tr>
<tr class="separator:a72599d9a15ce1965a2df71d10817f5f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7cbdb3712481e3545cd557c4707e04ba"><td class="memItemLeft" align="right" valign="top">__IM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structTPIU__Type.html#a7cbdb3712481e3545cd557c4707e04ba">FIFO0</a></td></tr>
<tr class="memdesc:a7cbdb3712481e3545cd557c4707e04ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xEEC (R/ ) Integration ETM Data.  <br /></td></tr>
<tr class="separator:a7cbdb3712481e3545cd557c4707e04ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae37fa30720fb17ecb4329088107370da"><td class="memItemLeft" align="right" valign="top">__IM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structTPIU__Type.html#ae37fa30720fb17ecb4329088107370da">FIFO1</a></td></tr>
<tr class="memdesc:ae37fa30720fb17ecb4329088107370da"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xEFC (R/ ) Integration ITM Data.  <br /></td></tr>
<tr class="separator:ae37fa30720fb17ecb4329088107370da"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a55906c9c7da8aebe414f7af4fbba867e"><td class="memItemLeft" align="right" valign="top">__IM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structTPIU__Type.html#a55906c9c7da8aebe414f7af4fbba867e">FSCR</a></td></tr>
<tr class="memdesc:a55906c9c7da8aebe414f7af4fbba867e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x308 (R/ ) Formatter Synchronization Counter Register.  <br /></td></tr>
<tr class="separator:a55906c9c7da8aebe414f7af4fbba867e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa5ad72117900f908adc6191a50b473c4"><td class="memItemLeft" align="right" valign="top">__IM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structTPIU__Type.html#aa5ad72117900f908adc6191a50b473c4">ITATBCTR0</a></td></tr>
<tr class="memdesc:aa5ad72117900f908adc6191a50b473c4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xEF8 (R/ ) ITATBCTR0.  <br /></td></tr>
<tr class="separator:aa5ad72117900f908adc6191a50b473c4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a20011f46af07ce925f0426acc37aa54e"><td class="memItemLeft" align="right" valign="top">__IM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structTPIU__Type.html#a20011f46af07ce925f0426acc37aa54e">ITATBCTR2</a></td></tr>
<tr class="memdesc:a20011f46af07ce925f0426acc37aa54e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xEF0 (R/ ) ITATBCTR2.  <br /></td></tr>
<tr class="separator:a20011f46af07ce925f0426acc37aa54e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2b5bae5fdb65f5a9a40277872b140199"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structTPIU__Type.html#a2b5bae5fdb65f5a9a40277872b140199">ITCTRL</a></td></tr>
<tr class="memdesc:a2b5bae5fdb65f5a9a40277872b140199"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xF00 (R/W) Integration Mode Control.  <br /></td></tr>
<tr class="separator:a2b5bae5fdb65f5a9a40277872b140199"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7a1690d4e23b47430627cae1fdc73e5a"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structTPIU__Type.html#a7a1690d4e23b47430627cae1fdc73e5a">SPPR</a></td></tr>
<tr class="memdesc:a7a1690d4e23b47430627cae1fdc73e5a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0F0 (R/W) Selected Pin Protocol Register.  <br /></td></tr>
<tr class="separator:a7a1690d4e23b47430627cae1fdc73e5a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a527a8d1d23f64b647cfc1266b1ff721a"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structTPIU__Type.html#a527a8d1d23f64b647cfc1266b1ff721a">SSPSR</a></td></tr>
<tr class="memdesc:a527a8d1d23f64b647cfc1266b1ff721a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x000 (R/ ) Supported Parallel Port Size Register.  <br /></td></tr>
<tr class="separator:a527a8d1d23f64b647cfc1266b1ff721a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2b6dc203a24b2d2ce46935cec1b073ec"><td class="memItemLeft" align="right" valign="top">__IM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structTPIU__Type.html#a2b6dc203a24b2d2ce46935cec1b073ec">TRIGGER</a></td></tr>
<tr class="memdesc:a2b6dc203a24b2d2ce46935cec1b073ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xEE8 (R/ ) TRIGGER.  <br /></td></tr>
<tr class="separator:a2b6dc203a24b2d2ce46935cec1b073ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>Structure type to access the Trace Port Interface Register (TPI). </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a id="a7d6b32aac67b18ded927392a83245ace" name="a7d6b32aac67b18ded927392a83245ace"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a7d6b32aac67b18ded927392a83245ace">&#9670;&#160;</a></span>ACPR</h2>

<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">__IOM uint32_t TPIU_Type::ACPR</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register. </p>

</div>
</div>
<a id="a65a5db46df2d49e4b7d0cb2a91f362fc" name="a65a5db46df2d49e4b7d0cb2a91f362fc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a65a5db46df2d49e4b7d0cb2a91f362fc">&#9670;&#160;</a></span>CLAIMCLR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IOM uint32_t TPIU_Type::CLAIMCLR</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Offset: 0xFA4 (R/W) Claim tag clear. </p>

</div>
</div>
<a id="acc42ffa5fe661df6339dc3e9a61f57d7" name="acc42ffa5fe661df6339dc3e9a61f57d7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#acc42ffa5fe661df6339dc3e9a61f57d7">&#9670;&#160;</a></span>CLAIMSET</h2>

<div class="memitem">
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        <tr>
          <td class="memname">__IOM uint32_t TPIU_Type::CLAIMSET</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Offset: 0xFA0 (R/W) Claim tag set. </p>

</div>
</div>
<a id="a6362b723d89dd97aa71d72e3ce94465b" name="a6362b723d89dd97aa71d72e3ce94465b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6362b723d89dd97aa71d72e3ce94465b">&#9670;&#160;</a></span>CSPSR</h2>

<div class="memitem">
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        <tr>
          <td class="memname">__IOM uint32_t TPIU_Type::CSPSR</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Offset: 0x004 (R/W) Current Parallel Port Size Register. </p>

</div>
</div>
<a id="afc5d82ae575c1437b46d7b3928357dc3" name="afc5d82ae575c1437b46d7b3928357dc3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#afc5d82ae575c1437b46d7b3928357dc3">&#9670;&#160;</a></span>DEVID</h2>

<div class="memitem">
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          <td class="memname">__IM uint32_t TPIU_Type::DEVID</td>
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      </table>
</div><div class="memdoc">

<p>Offset: 0xFC8 (R/ ) TPIU_DEVID. </p>

</div>
</div>
<a id="a06cd44ff1439b93aff76a8d155d7b465" name="a06cd44ff1439b93aff76a8d155d7b465"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a06cd44ff1439b93aff76a8d155d7b465">&#9670;&#160;</a></span>DEVTYPE</h2>

<div class="memitem">
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          <td class="memname">__IM uint32_t TPIU_Type::DEVTYPE</td>
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</div><div class="memdoc">

<p>Offset: 0xFCC (R/ ) TPIU_DEVTYPE. </p>

</div>
</div>
<a id="aa151f4dedec63032b8d66830529bdbd4" name="aa151f4dedec63032b8d66830529bdbd4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aa151f4dedec63032b8d66830529bdbd4">&#9670;&#160;</a></span>FFCR</h2>

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          <td class="memname">__IOM uint32_t TPIU_Type::FFCR</td>
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<p>Offset: 0x304 (R/W) Formatter and Flush Control Register. </p>

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<a id="a72599d9a15ce1965a2df71d10817f5f8" name="a72599d9a15ce1965a2df71d10817f5f8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a72599d9a15ce1965a2df71d10817f5f8">&#9670;&#160;</a></span>FFSR</h2>

<div class="memitem">
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          <td class="memname">__IM uint32_t TPIU_Type::FFSR</td>
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</div><div class="memdoc">

<p>Offset: 0x300 (R/ ) Formatter and Flush Status Register. </p>

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<a id="a7cbdb3712481e3545cd557c4707e04ba" name="a7cbdb3712481e3545cd557c4707e04ba"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a7cbdb3712481e3545cd557c4707e04ba">&#9670;&#160;</a></span>FIFO0</h2>

<div class="memitem">
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          <td class="memname">__IM uint32_t TPIU_Type::FIFO0</td>
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<p>Offset: 0xEEC (R/ ) Integration ETM Data. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ae37fa30720fb17ecb4329088107370da">&#9670;&#160;</a></span>FIFO1</h2>

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<p>Offset: 0xEFC (R/ ) Integration ITM Data. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a55906c9c7da8aebe414f7af4fbba867e">&#9670;&#160;</a></span>FSCR</h2>

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<p>Offset: 0x308 (R/ ) Formatter Synchronization Counter Register. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aa5ad72117900f908adc6191a50b473c4">&#9670;&#160;</a></span>ITATBCTR0</h2>

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<p>Offset: 0xEF8 (R/ ) ITATBCTR0. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a20011f46af07ce925f0426acc37aa54e">&#9670;&#160;</a></span>ITATBCTR2</h2>

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<p>Offset: 0xEF0 (R/ ) ITATBCTR2. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a2b5bae5fdb65f5a9a40277872b140199">&#9670;&#160;</a></span>ITCTRL</h2>

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<p>Offset: 0xF00 (R/W) Integration Mode Control. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a7a1690d4e23b47430627cae1fdc73e5a">&#9670;&#160;</a></span>SPPR</h2>

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<p>Offset: 0x0F0 (R/W) Selected Pin Protocol Register. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a527a8d1d23f64b647cfc1266b1ff721a">&#9670;&#160;</a></span>SSPSR</h2>

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<p>Offset: 0x000 (R/ ) Supported Parallel Port Size Register. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a2b6dc203a24b2d2ce46935cec1b073ec">&#9670;&#160;</a></span>TRIGGER</h2>

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<p>Offset: 0xEE8 (R/ ) TRIGGER. </p>

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